Roof top terrace with Willamette River viewsĪmpere is designing the future of hyperscale cloud and edge computing with the world’s first cloud native processor.On-site bike parking and repair station.Walking distance of breweries, landscaped parks, art galleries, restaurants and shops.Unlimited Flextime and 10+ paid holidays.Standing desks/Ergo friendly desk set-up.Walking distance to restaurants, shops, Light rail, and train stations.Garage parking, including charging stations and bike parking.Office has panoramic views of Silicon Valley.Familiar in identifying and addressing issues often found at the chip level, some of which include:.Familiarity with Physical Verification flow automation.Shell, Skill, Calibre and other programming knowledge.Familiarity with Cadence and Mentor tools is required.Background with FinFets and double exposure metallization is highly desired.Work with multiple sites in a team environment, particularly with offices in the US, India, and Vietnam.Support on DRC fixes for FinFet designs.Support on metal-fill and density check for all partitions and at the chip-level.Support all PDV sign-off scripts at partition and at chip-level.Execute and debug final verification flows in preparation for gds tape out delivery (DRC, LVS, DFM, Antenna, Density Fill Routines, XOR, etc.).Responsibilities include partition and chip-level level ownership of physical design verification (PDV), and physical design reviews.As a member of the PDV Team, you’ll own chip-level physical design verification, physical verification flow automation, and physical design reviews

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